 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ordering number : en6144 51099rm (ot) no. 6144-1/43 LC75817E, 75817w sanyo electric co.,ltd. semiconductor company tokyo office tokyo bldg., 1-10, 1 chome, ueno, taito-ku, tokyo, 110-8534 japan 1/8 to 1/10 duty dot matrix lcd display controller/driver with key input function cmos ic any and all sanyo products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft? control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo representative nearest you before using any sanyo products described or contained herein in such applications. sanyo assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo products described or contained herein. ccb is a trademark of sanyo electric co., ltd. ccb is sanyo? original bus format and all the bus addresses are controlled by sanyo. overview the LC75817E and lc75817w are 1/8 to 1/10 duty dot matrix lcd display controller/drivers that supports the display of characters, numbers, and symbols. in addition to generating dot matrix lcd drive signals based on data transferred serially from a microcontroller, the LC75817E and lc75817w also provide on-chip character display rom and ram to allow display systems to be implemented easily. these products also provide up to 4 general-purpose output ports and incorporate a key scan circuit that accepts input from up to 30 keys to reduce printed circuit board wiring. features key input function for up to 30 keys (a key scan is performed only when a key is pressed.) controls and drives a 5 7, 5 8, or 5 9 dot matrix lcd. supports accessory display segment drive (up to 60 segments) display technique: 1/8 duty 1/4 bias drive (5 7 dots) 1/9 duty 1/4 bias drive (5 8 dots) 1/10 duty 1/4 bias drive (5 9 dots) display digits: 12 digits 1 line (5 7 dots, 5 8 dots) 11 digits 1 line (5 9 dots) display control memory cgrom: 240 characters (5 7, 5 8, or 5 9 dots) cgram: 16 characters (5 7, 5 8, or 5 9 dots) adram: 12 5 bits dcram: 48 8 bits instruction function display on/off control display shift function sleep mode can be used to reduce current drain. built-in display contrast adjustment circuit up to 4 general-purpose output ports are included. serial data i/o supports ccb format communication with the system controller. independent lcd drive block power supply vlcd a voltage detection type reset circuit is provided to initialize the ic and prevent incorrect display. the inh pin is provided. this pin turns off the display, disables key scanning, and forces the general-purpose output ports to the low level. rc oscillator circuit
package dimensions unit: mm 3151-qfp100e unit: mm 3181b-sqfp100 no. 6144-2/43 LC75817E, 75817w 21.6 0.8 3.0max 1.6 17.2 0.825 130 31 50 51 80 81 1.6 0.575 0.575 0.15 2.7 15.6 0.3 20.0 23.2 14.0 0.65 0.825 100 0.8 0.65 0.1 sanyo: qfp100e [LC75817E] 0.2 1.0 1.0 16.0 14.0 0.5 16.0 14.0 0.5 1.0 1.0 0.145 1.4 1.6max 0.5 0.5 100 125 26 50 51 75 76 0.1 sanyo: sqfp100 [lc75817w] no. 6144-3/43 LC75817E, 75817w pin assignments (top view) LC75817E qfp100e lc75817w sqfp100 no. 6144-4/43 LC75817E, 75817w parameter symbol conditions ratings unit maximum supply voltage v dd max v dd ?.3 to +7.0 v v lcd max v lcd ?.3 to +11.0 v v in 1 ce, cl, di, inh ?.3 to +7.0 v input voltage v in 2 osci, ki1 to ki5, test ?.3 to v dd + 0.3 v v in 3v lcd 1, v lcd 2, v lcd 3, v lcd 4 ?.3 to v lcd + 0.3 v v out 1 do ?.3 to +7.0 v output voltage v out 2 osco, ks1 to ks6, p1 to p4 ?.3 to v dd + 0.3 v v out 3v lcd 0, s1 to s60, com1 to com10 ?.3 to v lcd + 0.3 v i out 1 s1 to s60 300 ? output current i out 2 com1 to com10 3 ma i out 3 ks1 to ks6 1 ma i out 4 p1 to p4 5 ma allowable power dissipation pd max ta = 85? 200 mw operating temperature topr ?0 to +85 ? storage temperature tstg ?5 to +125 ? specifications absolute maximum ratings at ta = 25?, v ss = 0 v parameter symbol conditions ratings unit min typ max v dd v dd 4.5 6.0 v supply voltage v lcd when the display contrast adjustment circuit is used. 7.0 10.0 v when the display contrast adjustment circuit is not used. 4.5 10.0 v output voltage v lcd 0v lcd 0v lcd 4+4.5 v lcd v v lcd 1v lcd 1 3/4 (v lcd 0 v lcd 4) v lcd 0v input voltage v lcd 2v lcd 2 2/4 (v lcd 0 v lcd 4) v lcd 0v v lcd 3v lcd 3 1/4 (v lcd 0 v lcd 4) v lcd 0v v lcd 4v lcd 4 0 1.5 v v ih 1 ce, cl, di, inh 0.8 v dd 6.0 v input high level voltage v ih 2 osci 0.7 v dd v dd v v ih 3 ki1 to ki5 0.6 v dd v dd v input low level voltage v il 1 ce, cl, di, inh, ki1 to ki5 0 0.2 v dd v v il 2 osci 0 0.3 v dd v recommended external resistance r osc osci, osco 33 k recommended external capacitance c osc osci, osco 220 pf guaranteed oscillation range f osc osc 150 300 600 khz data setup time t ds cl, di: figure 2 160 ns data hold time t dh cl, di: figure 2 160 ns ce wait time t cp ce, cl: figure 2 160 ns ce setup time t cs ce, cl: figure 2 160 ns ce hold time t ch ce, cl: figure 2 160 ns high level clock pulse width t? cl: figure 2 160 ns low level clock pulse width t? cl: figure 2 160 ns do output delay time t dc do, r pu = 4.7k , c l = 10pf: figure 2 * 1 1.5 ? do rise time t dr do, r pu = 4.7k , c l = 10pf: figure 2 * 1 1.5 ? allowable operating ranges at ta = ?0 to +85?, v ss = 0 v note: * 1. since the do pin is an open-drain output, these times depend on the values of the pull-up resistor r pu and the load capacitance c l . no. 6144-5/43 LC75817E, 75817w parameter symbol conditions ratings unit min typ max hysteresis v h ce, cl, di, inh, ki1 to ki5 0.1 v dd v power-down detection voltage v det 2.5 3.0 3.5 v input high level current i ih ce, cl, di, inh, osci: v i = 6.0 v 5.0 ? input low level current i il ce, cl, di, inh, osci: v i = 0 v ?.0 ? input floating voltage v if ki1 to ki5 0.05 v dd v pull-down resistance r pd ki1 to ki5: v dd = 5.0 v 50 100 250 k output off leakage current i offh do: v o = 6.0 v 6.0 ? v oh 1 s1 to s60: i o = ?0 ? v lcd 0 ?0.6 v v oh 2 com1 to com10: i o = ?00 ? v lcd 0 ?0.6 v output high level voltage v oh 3 ks1 to ks6: i o = ?00 ? v dd ?1.0 v dd ?0.5 v dd ?0.2 v v oh 4 p1 to p4: i o = ? ma v dd ?1.0 v v oh 5 osco: i o = ?00 ? v dd ?1.0 v v ol 1 s1 to s60: i o = 20 ? v lcd 4 + 0.6 v v ol 2 com1 to com10: i o = 100 ? v lcd 4 + 0.6 v output low level voltage v ol 3 ks1 to ks6: i o = 25 ? 0.2 0.5 1.5 v v ol 4 p1 to p4: i o = 1 ma 1.0 v v ol 5 osco: i o = 500 ? 1.0 v v ol 6 do: i o = 1 ma 0.1 0.5 v v mid 1 s1 to s60: i o ?0 ? 2/4 (v lcd 0 ?v lcd 4) ?0.6 2/4 (v lcd 0 ?v lcd 4) + 0.6 v output middle level voltage * 2 v mid 2 com1 to com10: i o = ?00 ? 3/4 (v lcd 0 ?v lcd 4) ?0.6 3/4 (v lcd 0 ?v lcd 4) + 0.6 v v mid 3 com1 to com10: i o = ?00 ? 1/4 (v lcd 0 ?v lcd 4) ?0.6 1/4 (v lcd 0 ?v lcd 4) + 0.6 v oscillator frequency f osc osci, osco: r osc = 33 k , c osc = 220 pf 210 300 390 khz i dd 1v dd : sleep mode 100 ? i dd 2v dd : v dd = 6.0 v, output open, f osc = 300 khz 500 1000 ? current drain i lcd 1v lcd : sleep mode 5 a i lcd 2 v lcd : v lcd = 10.0 v, output open, f osc = 300 khz 450 900 ? when the display contrast adjustment circuit is used. i lcd 3 v lcd : v lcd = 10.0 v, output open, f osc = 300 khz 200 400 ? when the display contrast adjustment circuit is not used. electrical characteristics for the allowable operating ranges note: * 2. excluding the bias voltage generation divider resistor built into the v lcd 0, v lcd 1, v lcd 2, v lcd 3, and v lcd 4. (see figure 1.) excluding these resistors to the common and segment drivers figure 1 no. 6144-6/43 LC75817E, 75817w ?when cl is stopped at the low level ?when cl is stopped at the high level block diagram figure 2 no. 6144-7/43 LC75817E, 75817w pin functions pin pin no. function active i/o handling when unused LC75817E lc75817w segment driver outputs. the s60/com10 pin can be used as common driver output under the ?et display technique?instruction. open ? s1 to s59 s60/com10 3 to 61 62 1 to 59 60 common driver outputs. open ? com1 to com9 71 to 63 69 to 61 oscillator connections. an oscillator circuit is formed by connecting an external resistor and capacitor at these pins. gnd ? osci 97 95 serial data interface connections to the controller. note that do, being an open-drain output, requires a pull-up resistor. ce : chip enable cl : synchronization clock di : transfer data do : output data gnd hi ce 100 98 i cl 1 99 ? di 2 100 open ? osco 96 94 input that turns the display off, disables key scanning, and forces the general-purpose output ports low. ?when inh is low (v ss ): display off s1 to s59 = ??(v lcd 4). s60/com10 = ??(v lcd 4). com1 to com9 = ??(v lcd 4). ?general-purpose output ports p1 to p4 = low (v ss ) ?key scanning disabled: ks1 to ks6 = low (v ss ) ?all the key data is reset to low. ?when inh is high (v dd ): display on the state of the general-purpose output ports can be set by executing a "set general-purpose output port state" instruction. key scanning is enabled. however, serial data can be transferred when the inh pin is low. v dd li inh 98 96 lcd drive 3/4 bias voltage (middle level) supply pin. this pin can be used to supply the 3/4 (v lcd 0 ?v lcd 4) voltage level externally. open ? v lcd 1 90 88 lcd drive 2/4 bias voltage (middle level) supply pin. this pin can be used to supply the 2/4 (v lcd 0 - v lcd 4) voltage level externally. open ? v lcd 2 91 89 lcd drive 1/4 bias voltage (middle level) supply pin. this pin can be used to supply the 1/4 (v lcd 0 ?v lcd 4) voltage level externally. open ? v lcd 3 92 90 logic block power supply connection. provide a voltage of between 4.5 and 6.0 v. v dd 87 85 lcd driver block power supply connection. provide a voltage of between 7.0 and 10.0 v when the display contrast adjustment circuit is used and provide a voltage of between 4.5 and 10.0 v when the circuit is not used. v lcd 88 86 power supply connection. connect to ground. v ss 94 92 key scan outputs. although normal key scan timing lines require diodes to be inserted in the timing lines to prevent shorts, since these outputs are unbalanced cmos transistor outputs, these outputs will not be damaged by shorting when these outputs are used to form a key matrix. open ? ks1 to ks6 72 to 77 70 to 75 key scan inputs. these pins have built-in pull-down resistors. gnd hi ki1 to ki5 78 to 82 76 to 80 general-purpose output ports open ? p1 to p4 83 to 86 81 to 84 do 99 97 o open this pin must be connected to ground. ? test 95 93 lcd drive 4/4 bias voltage (high level) supply pin. the level on this pin can be changed by the display contrast adjustment circuit. however, (v lcd 0 ?v lcd 4) must be greater than or equal to 4.5 v. also, external power must not be applied to this pin since the pin circuit includes the display contrast adjustment circuit. open o v lcd 0 89 87 lcd drive 0/4 bias voltage (low level) supply pin. fine adjustment of the display contrast can be implemented by connecting an external variable resistor to this pin. however, (v lcd 0 ?v lcd 4) must be greater than or equal to 4.5 v, and vlcd4 must be in the range 0 v to 1.5 v, inclusive. gnd ? v lcd 4 93 91 no. 6144-8/43 LC75817E, 75817w block functions ac (address counter) ac is a counter that provides the addresses used for dcram and adram. the address is automatically modified internally, and the lcd display state is retained. dcram (data control ram) dcram is ram that is used to store display data expressed as 8-bit character codes. (these character codes are converted to 5 7, 5 8, or 5 9 dot matrix character patterns using cgrom or cgram.) dcram has a capacity of 48 8 bits, and can hold 48 characters. the table below lists the correspondence between the 6-bit dcram address loaded into ac and the display position on the lcd panel. when the dcram address loaded into ac is 00 h . display digit 1 2 3 4 56789101112 dcram address (hexadecimal) 00 01 02 03 04 05 06 07 08 09 0a 0b however, when the display shift is performed by specifying mdata, the dcram address shifts as shown below. note: * 3. the dcram addresses are expressed in hexadecimal. example: when the dcram address is 2e h . note: * 4. 5 7 dots ... 12-digit display 5 7 dots 5 8 dots ... 12-digit display 5 8 dots 5 9 dots ... 12-digit display 4 9 dots display digit 1 2 3 4 56789101112 dcram address (hexadecimal) 01 02 03 04 05 06 07 08 09 0a 0b 0c (left shift) display digit 1 2 3 4 56789101112 dcram address (hexadecimal) 2f 00 01 02 03 04 05 06 07 08 09 0a dcram address da0 da1 da2 da3 da4 da5 (right shift) least significant bit lsb da0 da1 da2 da3 da4 da5 011101 most significant bit msb hexadecimal hexadecimal no. 6144-9/43 LC75817E, 75817w adram (additional data ram) adram is ram used to store the adata display data. adram has a capacity of 12 5 bits, and the stored display data is displayed directly without the use of cgrom or cgram. the table below lists the correspondence between the 4-bit adram address loaded into ac and the display position on the lcd panel. when the adram address loaded into ac is 0 h . (number of digit displayed: 12) display digit 1 2 3 4 56789101112 adram address (hexadecimal) 0 1 2 3 456789ab however, when the display shift is performed by specifying adata, the adram address shifts as shown below. display digit 1 2 3 4 56789101112 adram address (hexadecimal) 1 2 3 4 56789ab0 (left shift) display digit 1 2 3 4 56789101112 adram address (hexadecimal) b 0 1 2 3456789a (right shift) note: * 5. the adram addresses are expressed in hexadecimal. example: when the adram address is a h note: * 6. 5 7 dots ... 12-digit display 5 dots 5 8 dots ... 12-digit display 5 dots 5 9 dots ... 12-digit display 4 dots cgrom (character generator rom) cgrom is rom used to generate the 240 kinds of 5 7, 5 8, or 5 9 dot matrix character patterns from the 8-bit character codes. cgrom has a capacity of 240 45 bits. when a character code is written to dcram, the character pattern stored in cgrom corresponding to the character code is displayed at the position on the lcd corresponding to the dcram address loaded into ac. cgram (character generator ram) cgram is ram to which user programs can freely write arbitrary character patterns. up to 16 kinds of 5 7, 5 8, or 5 9 dot matrix character patterns can be stored. cgram has a capacity of 16 45 bits. adram address ra0 ra1 ra2 ra3 ra0 ra1 ra2 ra3 0101 hexadecimal least significant bit lsb most significant bit msb no. 6144-10/43 LC75817E, 75817w serial data input ?when cl is stopped at the low level ?when cl is stopped at the high level b0 to b3, a0 to a3: ccb address 42h d0 to d63: instruction data the data is acquired on the rising edge of the cl signal and latched on the falling edge of the ce signal. when transferring instruction data from the microcontroller, applications must assure that the time from the transfer of one set of instruction data until the next instruction data transfer is significantly longer than the instruction execution time. instruction data (up to 64 bits) instruction data (up to 64 bits) no. 6144-11/43 LC75817E, 75817w instruction table notes: * 7. the data format differs when the ?cram data write?instruction is executed in the increment mode (im = 1). (see detailed instruction descriptions .) * 8. the data format differs when the ?dram data write?instruction is executed in the increment mode (im = 1). (see detailed instruction descriptions.) * 9. the execution times listed here apply when fosc = 300 khz. the execution times differ when the oscillator frequency fosc diff ers. example: when fosc = 210 khz 300 27 ? = 39 ? 210 * 10.when the sleep mode (sp = 1) is set, the execution time is 27 ? (when f osc = 300 khz). instruction d0 d1...d39 d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 execution time * 9 set display technique display on/off control dg1 dg2 dg3 dg4 dg5 dg6 dg7 dg8 dg9 dg10 dg11 dg12 xxxx display shift set ac address da0 da1 da2 da3 da4 da5 x x dcram data write * 7 ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 da0 da1 da2 da3 da4 da5 x x adram data write * 8 ad1ad2ad3ad4ad5xxxra0ra1ra2ra3xxxx cgram data write cd1 cd2...cd40 cd41 cd42 cd43 cd44 cd45 x x x ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 set display contrast ct0ct1ct2ct3xxxx set key scan output state kc1 kc2 kc3 kc4 kc5 kc6 x x set general-purpose output port state d56 d57 d58 d59 d60 d61 d62 d63 dt1 dt2 x x 0 0 0 1 0 ? m a sc sp 0 0 1 0 0 ?/27 ? * 10 m a r/l x 0 0 1 1 27 ? ra0 ra1 ra2 ra3 0 1 0 0 27 ? im x x x 0 1 0 1 27 ? im x x x 0 1 1 0 27 ? x x x x 0 1 1 1 27 ? ctc x x x 1 0 0 0 0 ? xxxx1001 0 s pc1 pc2 pc3 pc4 1 0 1 0 0 ? x: don? care no. 6144-12/43 LC75817E, 75817w detailed instruction descriptions set display technique ... no. 6144-13/43 LC75817E, 75817w sc: controls the common and segment output pins note: * 13. when sc is 1, the s1 to s60 and com1 to com10 output pins are set to the v lcd 4 level, regardless of the m, a, and dg1 to dg12 data. sc common and segment output pin states 0 output of lcd drive waveforms 1 fixed at the v lcd 4 level (all segments off) sp: controls the normal mode and sleep mode sp mode 0 normal mode sleep mode 1 the common and segment pins go to the v lcd 4 level and the oscillator on the osci, osco pins is stopped (although it operates during key scan operations) to reduce current drain. although the ?isplay on/off control? ?et display contrast? ?et key scan output s tate? and ?et general-purpose output port state?instructions can be executed in this mode, applications must return the ic to normal mode to execute any of the other instruction settings. ?display shift ... no. 6144-14/43 LC75817E, 75817w x: don? care ?dcram data write ... no. 6144-15/43 LC75817E, 75817w x: don? care data format at (1) (24 bits) code d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 ac0 ac1 ac2 ac3 ac4 ac5 ac6 ac7 da0 da1 da2 da3 da4 da5 x x im x x x d60 d61 d62 d63 0101 x: don? care ?adram data write ... no. 6144-16/43 LC75817E, 75817w im: setting the method of writing data to adram im adram data write method 0 normal adram data write (specifies the adram address and writes the adram data.) 1 increment mode adram data write (increments the adram address by +1 each time data is written to adram.) notes: *15. ?adram data write method when im = 0 ?adram data write method when im = 1 (instructions other than the ?dram data write?instruction cannot be excuted.) x: don? care x: don? care data format at (4) (24 bits) code d40 d41 d42 d43 d44 d45 d46 d47 d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 ad1 ad2 ad3 ad4 ad5 x x x ra0 ra1 ra2 ra3 x x x x im x x x d60 d61 d62 d63 0110 x: don? care data format at (6) (16 bits) code d48 d49 d50 d51 d52 d53 d54 d55 d56 d57 d58 d59 d60 d61 d62 d63 ad1 ad2 ad3 ad4 ad5 x x x 0 x x x 0 1 1 0 data format at (5) (8 bits) code d56 d57 d58 d59 d60 d61 d62 d63 ad1 ad2 ad3 ad4 ad5 x x x adram data write finishes ccb address ccb address ccb address ccb address adram data write finishes adram data write finishes adram data write finishes instruction execution time instruction execution time instruction execution time instruction execution time 24 bits 24 bits 24 bits 24 bits (4) (4) (4) (4) ccb address ccb address ccb address ccb address ccb address ccb address 24 bits 8 bits 8 bits 8 bits 8 bits 16 bits instruction execution time instruction execution time instruction execution time instruction execution time instruction execution time instruction execution time adram data write finishes adram data write finishes adram data write finishes adram data write finishes adram data write finishes adram data write finishes instructions other than the ?dram data write?instruction cannot be excuted. (4) (5) (5) (5) (5) (6) no. 6144-17/43 LC75817E, 75817w x: don? care ?cgram data write ... note that although the display contrast can be adjusted by operating the built-in display contrast adjustment circuit, it is al so possible to apply fine adjustments to the contrast by connecting an external variable resistor to the v lcd 4 pin and modifying the v lcd 4 pin voltage. however, the following conditions must be met: (v lcd 0 ?v lcd 4) 3 4.5 v, and 1.5 v 3 v lcd 4 3 0 v. no. 6144-18/43 LC75817E, 75817w ?set display contrast ... no. 6144-19/43 LC75817E, 75817w ?set key scan output state ... no. 6144-20/43 LC75817E, 75817w serial data output ?when cl is stopped at the low level ?when cl is stopped at the high level b0 to b3, a0 to a3 : ccb address 43h kd1 to kd30 : key data sa : sleep acknowledge data note: *17. if a key data read operation is executed when do is high, the read key data (kd1 to kd30) and sleep acknowledge data(sa) will be invalid. no. 6144-21/43 LC75817E, 75817w output data kd1 to kd30 : key data when a key matrix of up to 30 keys is formed from the ks1 to ks6 output pins and the ki1 to ki5 input pins and one of those keys is pressed, the key output data corresponding to that key will be set to 1. the table shows the relationship between those pins and the key data bits. when the states of the ks1 to ks6 output pins during key scan standby are set to low for ks1 and ks2 and to high for ks3 to ks6 with the ?et key scan output state?instruction and a key matrix of up to 20 keys is formed from the ks3 to ks6 output pins and the ki1 to ki5 input pins, the kd1 to kd10 key data bits will be set to 0. sa : sleep acknowledge data this output data bit is set to the state when the key was pressed. also, while do will be low in this case, if serial data is input and the mode is set (to normal or sleep mode) during this period, that mode will be set. sa will be 1 in sleep mode and 0 in normal mode. ki1 ki2 ki3 ki4 ki5 ks1 kd1 kd2 kd3 kd4 kd5 ks2 kd6 kd7 kd8 kd9 kd10 ks3 kd11 kd12 kd13 kd14 kd15 ks4 kd16 kd17 kd18 kd19 kd20 ks5 kd21 kd22 kd23 kd24 kd25 ks6 kd26 kd27 kd28 kd29 kd30 no. 6144-22/43 LC75817E, 75817w in normal mode the pins ks1 to ks6 are set to high or low with the ?et key scan output state?instruction. if a key on one of the lines corresponding to a ks1 to ks6 pin which is set high is pressed, a key scan is started and the keys are scanned until all keys are released. multiple key presses are recognized by determining whether multiple key data bits are set. if a key is pressed for longer than 4800t(s) (where t= ) the LC75817E/w outputs a key data read request (a low level on do) to the controller. the controller acknowledges this request and reads the key data. however, if ce is high during a serial data transfer, do will be set high. after the controller reads the key data, the key data read request is cleared (do is set high) and the LC75817E/w performs another key scan. also note that do, being an open-drain output, requires a pull-up resistor (between 1 and 10 k ). note: * 18. note that the high/low states of these pins are determined by the ?et key scan output state? instruction, and that key sc an output signals are not output from pins that are set to low. 1 fosc key scan operation functions key scan timing the key scan period is 2304t(s). to reliably determine the on/off state of the keys, the LC75817E/w scans the keys twice and determines that a key has been pressed when the key data agrees. it outputs a key data read request (a low level on do) 4800t(s) after starting a key scan. if the key data dose not agree and a key was pressed at that point, it scans the keys again. thus the LC75817E/w cannot detect a key press shorter than 4800t(s). * 18 * 18 * 18 * 18 * 18 * 18 * 18 * 18 * 18 * 18 * 18 * 18 4608t(s) key input 1 key input 2 key scan ce di do 4800t(s) 4800t(s) 4800t(s) serial data transfer serial data transfer key address (43h) serial data transfer key address key data read request key data read key data read request key data read request t= 1 fosc key data read key data read key address ks1 ks2 ks3 ks4 ks5 ks6 key on t= 1 fosc no. 6144-23/43 LC75817E, 75817w in sleep mode the pins ks1 to ks6 are set to high or low with the ?et key scan output state?instruction. if a key on one of the lines corresponding to a ks1 to ks6 pin which is set high is pressed, the oscillator on the osci, osco pins is started and a key scan is performed. keys are scanned until all keys are released. multiple key presses are recognized by determining whether multiple key data bits are set. if a key is pressed for longer than 4800t(s)(where t= ) the LC75817E/w outputs a key data read request (a low level on do) to the controller. the controller acknowledges this request and reads the key data. however, if ce is high during a serial data transfer, do will be set high. after the controller reads the key data, the key data read request is cleared (do is set high) and the LC75817E/w performs another key scan. however, this dose not clear sleep mode. also note that do, being an open-drain output, requires a pull-up resistor (between 1 and 10 k ). sleep mode key scan example example: when a ?isplay on/off control (sp = 1)?instruction and a ?et key scan output state (kc1 to kc5 = 0, kc6 = 1)?instruction are executed (i.e. sleep mode with only ks6 high) multiple key presses although the LC75817E/w is capable of key scanning without inserting diodes for dual key presses, triple key presses on the ki1 to ki5 input pin lines, or multiple key presses on the ks1 to ks6 output pin lines, multiple presses other than these cases may result in keys that were not pressed recognized as having been pressed. therefore, a diode must be inserted in series with each key. applications that do not recognize multiple key presses of three or more keys should check the key data for three or more 1 bits and ignore such data. 1 fosc note: * 19. these diodes are required to reliably recognize multiple key presses on the ks6 line when sleep mode state with only ks6 hi gh, as in the above example. that is, these diodes prevent incorrect operations due to sneak currents in the ks6 key scan output signal when keys o n the ks1 to ks5 lines are pressed at the same time. ??ks1 ??ks2 ??ks3 ??ks4 ??ks5 ??ks6 ki1 ki2 ki3 ki4 ki5 when any one of these keys is pressed, the oscillator on the osci, osco pins is started and the keys are scanned. * 19 key input (ks6 line) key scan ce di do 4800t(s) 4800t(s) serial data transfer serial data transfer key address (43h) serial data transfer key address key data read request key data read key data read request t= 1 fosc key data read no. 6144-24/43 LC75817E, 75817w 1/8 duty, 1/4 bias drive technique lcd driver output when all lcd segments corresponding to com1 to com8 are turned on lcd driver output when all lcd segments corresponding to com1 to com8 are turned off lcd driver output when only lcd segments corresponding to com1 are turned on lcd driver output when only lcd segments corresponding to com2 are turned on vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 no. 6144-25/43 LC75817E, 75817w 1/9 duty, 1/4 bias drive technique lcd driver output when all lcd segments corresponding to com1 to com9 are turned on lcd driver output when all lcd segments corresponding to com1 to com9 are turned off lcd driver output when only lcd segments corresponding to com1 are turned on lcd driver output when only lcd segments corresponding to com2 are turned on vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 no. 6144-26/43 LC75817E, 75817w 1/10 duty, 1/4 bias drive technique lcd driver output when all lcd segments corresponding to com1 to com10 are turned on lcd driver output when all lcd segments corresponding to com1 to com10 are turned off lcd driver output when only lcd segments corresponding to com1 are turned on lcd driver output when only lcd segments corresponding to com2 are turned on vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 vlcd0 vlcd4 no. 6144-27/43 LC75817E, 75817w voltage detection type reset circuit (vdet) this circuit generates an output signal and resets the system when logic block power is first applied and when the voltage drops, i.e., when the logic block power supply voltage is less than or equal to the power down detection voltage vdet, which is 3.0v, typical. to assure that this function operates reliably, a capacitor must be added to the logic block power supply line so that the logic block power supply voltage v dd rise time when the logic block power is first applied and the logic block power supply voltage v dd fall time when the voltage drops are both at least 1 ms. (see figure 3.) power supply sequence the following sequences must be observed when power is turned on and off. (see figure 3.) power on :logic block power supply(v dd ) on ? lcd driver block power supply(v lcd ) on power off:lcd driver block power supply(v lcd ) off ? logic block power supply(v dd ) off however, if the logic and lcd driver blocks use a shared power supply, then the power supplies can be turned on and off at the same time. system reset 1. reset function the LC75817E/w performs a system reset with the vdet. when a system reset is applied, the display is turned off, key scanning is disabled, the key data is reset, and the general-purpose ports are set to and held at the low level (v ss ). these states that are created as a result of the system reset can be cleared by executing the instruction described below. (see figure 3.) clearing the display off state display operation can be enabled by executing a ?isplay on/off control?instruction. however, since the contents of the dcram, adram, and cgram are undefined, applications must set the contents of these memories before turning on display with the ?isplay on/off control?instruction. that is, applications must execute the following instructions. set display technique dcram data write adram data write (if the adram is used.) cgram data write (if the cgram is used.) set ac address set display contrast (if the display contrast adjustment circuit is used.) after executing the above instructions, applications must turn on the display with a ?isplay on/off control?instruction. note that when applications turn off in the normal mode, applications must turn off the display with a ?isplay on/off control?instruction or the inh pin. ?clearing the key scan disable and key data reset states executing a ?et key scan output state?instruction not only creates a state in which key scanning can be performed, but also clears the key data reset. ?clearing the general-purpose output ports locked at the low level (v ss ) state executing a ?et general-purpose output port state?instruction clears the general-purpose output ports locked at the low level (v ss ) state and sets the states of the general-purpose output ports. no. 6144-28/43 LC75817E, 75817w ?t1 3 1 ms (logic block power supply voltage v dd rise time) ?t2 3 0 ms ?t3 3 0 ms ?t4 3 1 ms (logic block power supply voltage v dd fall time) ?initial state settings set display technique dcram data write adram data write (if the adram is used.) cgram data write (if the cgram is used.) set ac address set display contrast (if the display contrast adjustment circuit is used.) instruction execution key scan general-purpose output ports display state initial state settings disabled execution enabled fixed at the low level (v ss ) can be set to either the high (v dd ) or low (v ss ) level. display off display on display off v dd v lcd vdet vdet t1 t2 t3 t4 ?et key scan output state?instruction execution ?et general-purpose output port state instruction execution ?isplay on/off control instruction execution (turning the display on) ?isplay on/off control instruction execution (turning the display off) figure 3 no. 6144-29/43 LC75817E, 75817w 2. block states during a system reset (1) clock generator, timing generator when a reset is applied, the oscillator on the osci, osco pins is started forcibly. this generates the base clock and enables instruction execution. (2) instruction register, instruction decoder when a reset is applied, these circuits are forcibly initialized internally. then, when instruction execution starts, the ic operates according to those instructions. (3) address register, address counter when a reset is applied, these circuits are forcibly initialized internally. then, the dcram and the adram addresses are set when ?et ac address?instruction is executed. (4) dcram, adram, cgram since the contents of the dcram, adram, and cgram become undefined during a reset, applications must execute ?cram data write? ?dram data write (if the adram is used.)? and ?gram data write (if the cgram is used.)?instructions before executing a ?isplay on/off control?instruction. (5) cgrom character patterns are stored in this rom. (6) latch although the value of the data in the latch is undefined during a reset, the adram, cgrom, and cgram data is stored by executing a ?isplay on/off control?instruction. (7) common driver, segment driver these circuits are forced to the display off state when a reset is applied. (8) contrast adjuster display contrast adjustment circuit operation is disabled when a reset is applied. after that, the display contrast can be set by executing a ?et display contrast?instruction. (9) key scan, key buffer when a reset is applied, these circuits are forcibly initialized internally, and key scan operation is disabled. also, the key data is all set to 0. after that, key scanning can be performed by executing a ?et key scan output state instruction. (10) general port the general-purpose output ports are fixed at the low level (v ss ) when a reset is applied. (11) ccb interface, shift register these circuits go to the serial data input wait state. no. 6144-30/43 LC75817E, 75817w 3. output pin states during the reset period notes: * 20. this output pin is forcibly set to its segment output function and held at the low level (v lcd 4). however, when a ?et display technique?instruction is executed, the segment output or the common output function is selected as specified by that instruction. * 21. since this output pin is an open-drain output, a pull-up resistor (between 1 k and 10 k ) is required. this pin is held at the high level even if a key data read operation is performed before executing a ?et key scan output state?instruction. output pin state during reset s1 to s59 l (v lcd 4) s60/com10 l (v lcd 4) * 20 com1 to com9 l (v lcd 4) ks1 to ks6 l (v ss ) p1 to p4 l (v ss ) do h * 21 blocks that are reset general port contrast adjuster common driver timing generator clock generator vdet segment driver key buffer key scan instruction decoder instruction register address counter address register no. 6144-31/43 LC75817E, 75817w sample application circuit 1 1/8 duty, 1/4 bias drive technique (for use with normal panels) notes: * 22. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75817E/w is reset by the vdet. * 23. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. * 24. if the inh pin is not used, it must be connected to the logic block power supply v dd . * 25. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. * 22 * 23 * 24 c 3 0.047 ? from the controller to the controller to the controller power supply key matrix (up to 30 keys) (general-purpose output ports) used with the backlight controller or other circuit lcd panel * 25 no. 6144-32/43 LC75817E, 75817w sample application circuit 2 1/8 duty, 1/4 bias drive technique (for use with large panels) * 22 * 23 * 24 c 3 0.047 ? 10 k 3 r 3 2.2 k from the controller to the controller to the controller power supply key matrix (up to 30 keys) (general-purpose output ports) used with the backlight controller or other circuit * 25 lcd panel notes: * 22. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75817E/w is reset by the vdet. * 23. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. * 24. if the inh pin is not used, it must be connected to the logic block power supply v dd . * 25. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. no. 6144-33/43 LC75817E, 75817w sample application circuit 3 1/9 duty, 1/4 bias drive technique (for use with normal panels) * 22 * 23 * 24 c 3 0.047 ? from the controller to the controller to the controller power supply key matrix (up to 30 keys) (general-purpose output ports) used with the backlight controller or other circuit * 25 lcd panel notes: * 22. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75817E/w is reset by the vdet. * 23. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. * 24. if the inh pin is not used, it must be connected to the logic block power supply v dd . * 25. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. no. 6144-34/43 LC75817E, 75817w sample application circuit 4 1/9 duty, 1/4 bias drive technique (for use with large panels) * 22 * 23 * 24 from the controller to the controller to the controller power supply key matrix (up to 30 keys) (general-purpose output ports) used with the backlight controller or other circuit * 25 lcd panel c 3 0.047 ? 10 k 3 r 3 2.2 k notes: * 22. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75817E/w is reset by the vdet. * 23. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. * 24. if the inh pin is not used, it must be connected to the logic block power supply v dd . * 25. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. no. 6144-35/43 LC75817E, 75817w sample application circuit 5 1/10 duty, 1/4 bias drive technique (for use with normal panels) * 22 * 23 * 24 from the controller to the controller to the controller power supply key matrix (up to 30 keys) (general-purpose output ports) used with the backlight controller or other circuit * 25 lcd panel c 3 0.047 ? notes: * 22. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75817E/w is reset by the vdet. * 23. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. * 24. if the inh pin is not used, it must be connected to the logic block power supply v dd . * 25. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. no. 6144-36/43 LC75817E, 75817w sample application circuit 6 1/10 duty, 1/4 bias drive technique (for use with large panels) * 22 * 23 * 24 from the controller to the controller to the controller power supply key matrix (up to 30 keys) (general-purpose output ports) used with the backlight controller or other circuit * 25 lcd panel c 3 0.047 ? 10 k 3 r 3 2.2 k notes: * 22. add a capacitor to the logic block power supply line so that the logic block power supply voltage v dd rise time when power is applied and the logic block power supply voltage v dd fall time when power drops are both at least 1 ms, as the LC75817E/w is reset by the vdet. * 23. if a variable resistor is not used for display contrast fine adjustment, the v lcd 4 pin must be connected to ground. * 24. if the inh pin is not used, it must be connected to the logic block power supply v dd . * 25. the do pin, being an open-drain output, requires a pull-up resistor. select a resistance (between 1 to 10 k ) appropriate for the capacitance of the external wiring so that signal waveforms are not degraded. no. 6144-37/43 LC75817E, 75817w sample correspondence between instructions and the display (when the lc75817-8720 is used) no. lsb instruction (hexadecimal) msb display operation d40 to d43 d44 to d47 d48 to d51 d52 to d55 d56 to d59 d60 to d63 1 power application initializes the ic. (initialization with the vdet.) the display is in the off state. 2 set display technique sets to 1/8 duty 1/4 bias display drive technique 08 3 dcram data write (increment mode) writes the display data ??to dcram address 00h 02001a 4 dcram data write (increment mode) writes the display data ??to dcram address 01h 35 5 dcram data write (increment mode) writes the display data ??to dcram address 02h 14 6 dcram data write (increment mode) writes the display data ??to dcram address 03h e4 7 dcram data write (increment mode) writes the display data ??to dcram address 04h 95 8 dcram data write (increment mode) writes the display data ??to dcram address 05h f4 9 dcram data write (increment mode) writes the display data ??to dcram address 06h 02 10 dcram data write (increment mode) writes the display data ??to dcram address 07h c4 11 dcram data write (increment mode) writes the display data ??to dcram address 08h 35 12 dcram data write (increment mode) writes the display data ??to dcram address 09h 94 13 dcram data write (increment mode) writes the display data ??to dcram address 0ah 02 14 dcram data write (increment mode) writes the display data ??to dcram address 0bh 02 15 dcram data write (increment mode) writes the display data ??to dcram address 0ch c4 16 dcram data write (increment mode) writes the display data ??to dcram address 0dh 34 17 dcram data write (increment mode) writes the display data ??to dcram address 0eh 73 18 dcram data write (increment mode) writes the display data ??to dcram address 0fh 53 19 dcram data write (increment mode) writes the display data ??to dcram address 10h 83 20 dcram data write (increment mode) writes the display data ??to dcram address 11h 13 21 dcram data write (increment mode) writes the display data ??to dcram address 12h 730a continued on next page. no. 6144-38/43 LC75817E, 75817w continued from preceding page. note: * 26. this example above assumes the use of 12 digits 5 7 dot matrix lcd. cgram and adram are not used. x: don? care no. lsb instruction (hexadecimal) msb display operation d40 to d43 d44 to d47 d48 to d51 d52 to d55 d56 to d59 d60 to d63 22 set ac address loads the dcram address 00h and the adram 0 0 0 2 address 0h into ac 23 display on/off control turns on the lcd for all digits (12 digits) in mdata fffx14 24 display shift shifts the display (mdata only) to the left 1c 25 display shift shifts the display (mdata only) to the left 1c 26 display shift shifts the display (mdata only) to the left 1c 27 display shift shifts the display (mdata only) to the left 1c 28 display shift shifts the display (mdata only) to the left 1c 29 display shift shifts the display (mdata only) to the left 1c 30 display shift shifts the display (mdata only) to the left 1c 31 display on/off control set to sleep mode, turns off the lcd for all digits 000x84 32 display on/off control turns on the lcd for all digits (12 digits) in mdata fffx14 33 set ac address loads the dcram address 00h and the adram 0 0 0 2 address 0h into ac s a n y o l s i s a n y o l s i l a n y o l s i l c n y o l s i l c 7 y o l s i l c 7 5 o l s i l c 7 5 8 l s i l c 7 5 8 1 l s i l c 7 5 8 1 7 l s i l c 7 5 8 1 7 s a n y o l s i no. 6144-39/43 LC75817E, 75817w notes on the controller key data read techniques 1. timer based key data acquisition ?flowchart ?timing chart t5: key scan execution time when the key data agreed for two key scans. (4800t(s)) t6: key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600t(s)) t7: key address (43h) transfer time t8: key data read time ?explanation in this technique, the controller uses a timer to determine key on/off states and read the key data. the controller must check the do state when ce is low every t9 period without fail. if do is low, the controller recognizes that a key has been pressed and executes the key data read operation. the period t9 in this technique must satisfy the following condition. t9>t6+t7+t8 if a key data read operation is executed when do is high, the read key data (kd1 to kd30) and sleep acknowledge data (sa) will be invalid. 1 t = fosc ce = l do = l key data read processing no yes key input key scan ce di do key on key on t5 t6 t5 t5 t8 t7 t7 t7 t8 t8 t9 t9 t9 t9 key address key data read key data read request controller determination (key on) controller determination (key on) controller determination (key off) controller determination (key on) controller determination (key off) no. 6144-40/43 LC75817E, 75817w 2. interrupt based key data acquisition ?flowchart ?timing chart t5: key scan execution time when the key data agreed for two key scans. (4800t(s)) t6: key scan execution time when the key data did not agree for two key scans and the key scan was executed again. (9600t(s)) t7: key address (43h) transfer time t8: key data read time 1 t = fosc ce = l do = l key data read processing ce = l do = h key off no no yes yes wait for at least t10 key input key scan ce di do key on key on t5 t6 t5 t5 t8 t7 t7 t7 t8 t8 t10 key address key data read controller determination (key on) controller determination (key off) controller determination (key on) controller determination (key on) controller determination (key on) t8 t7 t10 t10 t10 controller determination (key off) key data read request no. 6144-41/43 LC75817E, 75817w ?explanation in this technique, the controller uses interrupts to determine key on/off states and read the key data. the controller must check the do state when ce is low. if do is low, the controller recognizes that a key has been pressed and executes the key data read operation. after that the next key on/off determination is performed after the time t10 has elapsed by checking the do state when ce is low and reading the key data. the period t10 in this technique must satisfy the following condition. t10 > t6 if a key data read operation is executed when do is high, the read key data (kd1 to kd30) and sleep acknowledge data (sa) will be invalid. no. 6144-42/43 LC75817E, 75817w lc75817-8720 character font (standard) a10735 ps no. 6144-43/43 lc75811e, 75811w this catalog provides information as of may, 1999. specifications and information herein are subject to change without notice. specifications of any and all sanyo products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer? products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer? products or equipment. sanyo electric co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo electric co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the ?elivery specification for the sanyo product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. |
Price & Availability of LC75817E
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |